IEEE

Three-Dimensional Room Transfer Function Parameterization Based on Multiple Concentric Planar Circular Arrays

Abstract: This study proposes a three-dimensional room transfer function (RTF) parameterization method based on multiple concentric planar circular arrays, which exhibits robustness to variations in ...
IEEE

Experimental Demonstration of Single-Pixel Imaging Using a Polarization-Maintaining Fiber Array With Four Fibers

Abstract: Endoscopes with small diameters are widely desired in medical and industrial fields. In this letter, we experimentally demonstrated single-pixel imaging (SPI) using a ...
GitHub

Description This project demonstrates the implementation of a Half Adder using Verilog HDL. It performs addition of two single-bit inputs and generates Sum and Carry outputs ...

This project implements a Half Adder using Verilog HDL. A Half Adder is a basic combinational circuit that adds two 1-bit inputs (A, B) and produces two outputs: Sum and Carry. The design is written ...